The memory industry is under constant pressure to both reduce component size as well as power requirements. One way that is being used to reduce component size is to fabricate memory devices as a three-dimensional (3D) memory device. This type of memory device can be achieved by forming a stack of memory cells vertically on a substrate, stacking a plurality of interconnected memory dies vertically within a single integrated circuit package, or some combination of these methods.
Multiple stacked memory dies in a memory package can be coupled (e.g., electrically connected) using vertical connectors, such as through silicon vias or other 3D conductive structures. Vias extend (at least partially) through a thickness of one or more of the dies and can be aligned when the dies are stacked, thus providing electrical communication among the dies in the stack. Such vias's are often formed of a conductive material, such as aluminum or copper.
In a stacked-die memory device, it is typically more efficient to combine controlling circuitry for each of the stacked memory dies of the memory package in a dedicated logic die. Thus, valuable real estate on each memory die that would normally be taken up by such controlling circuitry can be used for, for example, additional I/O instead.
One problem with having a memory device with a dedicated logic die is that the memory die of the stack conventionally utilize a fixed signaling interface. Accordingly, memory die made for use in a memory device utilizing a particular signaling interface can conventionally not be used in memory devices that utilize a different signaling interface.